1. Field of the Invention
The present invention relates to a surge protection circuit for semiconductor devices, particularly suitable for use in active matrix liquid crystal displays.
2. Description of the Related Art
Japanese Patent Publication 11-119256 discloses a surge protection circuit for a TFT (thin-film transistor) array of liquid crystal display elements connected to intersections of vertical and horizontal signal lines. The drains of all switching transistors are respectively connected to the vertical signal lines and the gates of all switching transistors are respectively connected to the horizontal signal lines. The prior art surge protection circuit is composed of a first array of bi-directional nonlinear circuits associated with the vertical lines and a second array of bi-directional nonlinear circuits associated with the horizontal lines. Each protection circuit is formed by a pair of first and second thin-film transistors. In each protection circuit, the drain and gate of the first transistor are connected together to a reference voltage terminal to which the source of the second transistor is also connected, and the drain and gate of the second transistor are connected together to the associated signal line to which the source of the first transistor is also connected. The vertical and horizontal signal lines are terminated at corresponding pad terminals. When high-voltage static energy builds up on a pad terminal of the LCD array, one of the associated transistors is turned to provide a low-impedance path for the static energy.
During manufacture of a protection transistor, an interlayer contact is established between the drain and the gate region by forming a contact hole (throughhole) in the gate insulator using a mask so that part of the gate region is exposed and depositing metal in the contact hole when the drain region is completed. Alternatively, after a gate and a drain region are formed, a contact hole is provided therebetween. Then, the gate and drain regions are connected through the contact hole when a transparent conductive film is deposited simultaneously with the deposition of the transparent conductive film for pixel electrodes.
Study has recently been undertaken to cut down the manufacturing cost of thin film transistor arrays by reducing masking processes. Since a masking process is used for establishing an interlayer contact between drain and gate electrodes, this cost reduction approach cannot be applied to the prior art surge protection circuit.
According to Japanese Patent Publication 6-18924, surge voltage is discharged through a path established between drain electrodes of adjacent signal lines, rather than through the gate-drain interlayer contact. This is achieved by separating signal lines at intervals of a few micrometers so that capacitive coupling is established between associated pad electrodes. When a high-voltage static surge develops, a potential difference occurs between adjacent signal lines and the surge is spark-discharged through the capacitive path and all signal lines are driven to the same potential. However, since the generation of a spark is necessary for discharging surge potentials, the protection circuit is not reliable.
It is therefore an object of the present invention to provide a surge protection transistor that can be fabricated with a reduced number of production steps.
The stated object is obtained by the provision of a floating-gate field effect transistor which is configured to form a low impedance path for a surge potential which builds up in a semiconductor device to be protected.
According to a first aspect of the present invention, there is provided a surge protection device comprising a gate electrode embedded in an insulator, a source electrode and a drain electrode on the insulator, the source and drain electrodes respectively forming first and second capacitances with the gate electrode, and a semiconductor island on the insulator. The semiconductor island forms a channel between the source and drain electrodes and a third capacitance with the gate electrode, the third capacitance being smaller than either of the first and second capacitances, the source and drain electrodes being adapted for connection to external circuitry for establishing a low-impedance path when the external circuitry is subjected to a surge potential.
According to a second aspect, the present invention provides a surge protection circuit comprising a plurality of surge protection devices. Each of the protection devices comprises a gate electrode embedded in an insulator, a source electrode and a drain electrode on the insulator, the source and drain electrodes respectively forming first and second capacitances with the gate electrode. A semiconductor island is formed on the insulator, the island forming a channel region between the source and drain electrodes and a third capacitance with the gate electrode, the third capacitance being smaller than either of the first and second capacitances.
The source and drain electrodes of each of the surge protection devices may be respectively connected to the drain and source electrodes of adjacent ones of the plurality of surge protection devices and further connected to pad electrodes of external circuitry for establishing connections with the adjacent surge protection devices when one of the pad electrodes is subjected to a surge potential. Alternatively, the source and drain electrodes of each of the surge protection devices may be connected in series to external circuitry for establishing a low-impedance path to ground when the external circuitry is subjected to a surge potential.
According to a third aspect, the present invention provides a surge protection circuit for a semiconductor display device. The display device includes a first plurality of pad electrodes, a plurality of vertical signal lines connected respectively to the first plurality of pad electrodes, a second plurality of pad electrodes, and a plurality of horizontal signal lines intersecting the vertical signal lines, the horizontal signal lines being connected respectively to the second plurality of pad electrodes. The surge protection circuit comprises a plurality of floating-gate field effect transistors. Each transistor includes a floating gate electrode, a source electrode and a drain electrode, the source and drain electrodes of each of the transistors being respectively connected to the drain and source electrodes of adjacent ones of the plurality of floating-gate transistors and further connected to the first plurality of pad electrodes for establishing connections with the adjacent floating-gate transistors when one of the first plurality of pad electrodes or one of the plurality of vertical signal lines is subjected to a surge potential. Alternatively, the source and drain electrodes of each of the transistors are respectively connected to the vertical signal lines for establishing a low-impedance path to ground when one of the first plurality of pad electrodes or one of the plurality of vertical signal lines is subjected to a surge potential.